A prior art transistor of the above-mentioned kind is shown in FIGS. 1a-1d. It is made in so-called SOS technique ("Silicon-On-Sapphire" technique). It is usually included in an integrated circuit with a large number of transistors, the different transistors being formed in separate silicon layers, arranged on a base of sapphire. Transistors of the opposite type--a P-transistor and an N-transistor--usually cooperate two and two in so-called CMOS circuits (complementary MOS circuits). Such a circuit is shown in FIGS. 1a to 1d.
FIG. 1a shows a section through a circuit of the above-mentioned kind. On the sapphire base 1 two rectangular silicon layers for transistors 2 and 3 are applied. The layer consists of a P-transistor 2 whose source 4 and drain 6 consist of highly doped P-conducting layers. The channel region 9 is a slightly N-doped layer. Above this and separated from the silicon by a thin insulating silicon dioxide layer 10, the control contact 11 of the transistor is arranged, which control contact consists of a layer of N-conducting polycrystalline silicon. The sapphire base and the transistor, with the exception of the contacted parts of the source and drain regions, are covered by a protective layer 12 of silicon dioxide. The source region 4 is contacted by a metal layer 13 and the drain region 6 by a metal layer 14.
The N-transistor 3 has heavily N-doped source and drain regions 22 and 20 and a channel region 24 which is slightly P-conducting. Above the channel region the control oxide layer 26 and the control electrode 27 are arranged. The transistor has a source contact 28, and its drain contact consists of the metal layer 14 which also constitutes a drain contact for the P-transistor 2.
FIG. 1b shows a section through the transistor 3, which section is perpendicular to the section in FIG. 1a and passes through the channel region 24. As will be clear from the figure, the control oxide layer 26 and the control contact 27 follow both the upper surface of the silicon layer and the two edge surfaces thereof.
FIG. 1c shows the transistor 3 with source and drain regions 22 and 20 and the channel region 24. The contact surfaces of the drain contact 14 and the source contact 28 with drain and source regions are shown in dashed lines. The control contact 27 is also shown in dashed lines.
FIG. 1d shows the circuit diagram of the CMOS transistor. The drain contacts of the transistors are electrically connected together since they consist of one and the same metal layer 14. The source contact 13 of the transistor 2 is connected to a positive supply voltage, and the source contact 28 of the transistor 3 is connected to a negative supply voltage. The control contacts 11 and 27 of the transistors are connected together and constitute the input of the circuit, to which an input signal Ui is supplied. The common drain contact 14 constitutes the output of the circuit, where the output signal Uu of the circuit is obtained.
In the known type of CMOS circuits described above, a space charge region occurs at the N-transistor at the junction between the drain and channel regions of the transistor. At sufficiently high supply voltage, electron hole pairs are formed in the space charge region. The holes travel to the channel region and cause this to become charged, which acts in the same way as a positive control voltage. The non-linearity caused thereby is a disadvantage in the case of analog operation of the CMOS circuit. It is known that this disadvantage may be reduced if the channel region is connected to the source region (is "grounded"). However, it has proved to be difficult to bring about an effective improvement in this way, primarily because the resistance between the source contact and the central parts of the channel region is high as a result of the weak doping of the region. For the same reason, known transistors of this kind possess less satisfactory high-frequency properties; further, they are impaired by noise caused by the surface state at the junction between the sapphire and the channel region.
Such a transistor is known from Patent Abstracts of Japan, abstract of JP No. 51-147186 (Fujitsu K. K.), Dec. 17, 1976. The superficial part of the channel region must have low doping--a doping dose of the order of magnitude of at most 10.sup.11 cm.sup.-2 --for the threshold voltage of the transistor to receive a useful value. The channel region of this known transistor is obviously homogeneous, i.e. with uniform doping within the entire region. This is the reason why this known transistor suffers from the disadvantages mentioned in the preceding paragraph.
A transistor of a similar kind is described in the IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, pages 198-201, which was published as late as in Feb. 1988.
From Patent Abstracts of Japan, abstract of JP No. 58-98969 (Nippon Denki K. K.), Jun. 13, 1983, a transistor is known which has a metal silicide layer nearest the substrate and partly below the channel region, the metal silicide layer being connected to the source contact of the transistor. The silicide layer is stated to provide elimination of certain parasitic effects. However, for reasons of manufacturing technique, it is difficult and complicated to manufacture a silicide layer of this kind, and such a layer involves a clear risk of leakage currents.
In known MOS transistors of the kind referred to here, it has proved that the highly doped source and drain regions tend to creep towards each other, during the manufacture, within that part of the silicon layer which is located at a greater depth below the surface. In these transistors, therefore, the length of the channel region must be kept greater than what would otherwise have been necessary.
Furthermore, it has been found that these known transistors are relatively sensitive to radiation. Radioactive radiation, for example gamma radiation, gives a positive charge of the sapphire, whereby an N-channel is induced in the surface of the slightly doped channel region, which surface faces the sapphire.
As will be clear from FIG. 1b, a transistor of the above kind consists of a main portion on the plane surface of the silicon layer and two "corner transistors" 31 and 32. Since the control electrode at the corners 31 and 32 influences the silicon layer from two directions, the effective threshold voltage will be lower (and the leakage currents higher) at the corners than on the plane surface of the transistor. It has also been found that the silicon oxide layer 26 becomes thicker at the edges below the corners 31 and 32. This causes the threshold voltage there to become more radiation-sensitive than for the main portion. Taken together, these effects at the corners and edges lead to a deterioration of the properties of the transistor as a whole. The requirements for accurate control of the manufacturing process will therefore be high to avoid that this deterioration becomes too great.